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3–6
Chapter 3: Specifications
Functional Description
When the register inputs/outputs parameter is turned off, the encoder takes one clock
cycle to encode a character. The encoded value—corresponding to the values of
datain and kin sampled by the encoder on rising edge n —is output shortly after
rising edge n , and is available to be sampled on the rising edge of clock cycle n+1 . (See
Figure 3–6 ).
Figure 3–5. Encoder Timing Diagram—Three Cycle Latency
clk
n
n+1 n+2 n+3
datain, kin, en, idle_ins
datao u t, rdo u t, kerr, v alid
rdforce, rdin
rdcascade
a
b
c
a
a
d
a
b
b
e
b
c
c
f
c
d
d
g
d
e
e
e
f
f
Figure 3–6. Encoder Timing Diagram—One Cycle Latency
clk
n
n+1
datain, kin, en, idle_ins
datao u t, rdo u t, kerr, v alid
rdforce, rdin
rdcascade
a
a
a
b
a
b
b
c
b
c
c
d
c
d
d
e
d
e
e
f
e
f
f
g
f
g
g
Fibre Channel and IEEE 802.3z 1000BaseX
In Fibre Channel and IEEE 802.3z 1000BaseX applications the encoder does not
automatically select the correct 8-bit data for Fibre Channel EOF or 1000BaseX Idle
ordered sets. The running disparity based selection of the correct 8-bit data must be
made before passing the data to the encoder.
Decoder
Data and identified 10-bit special K codes are converted from 10 bits to 8 bits; see
Table 3–1 on page 3–3 for a list of the valid K codes, and Figure 3–1 on page 3–1 for an
illustration of the conversion process.
When special 10-bit K codes are received, the special K codes are translated to 8-bit
values, and the kout signal is asserted. The decoder also checks for invalid 10-bit
codes.
When the decoder receives an invalid code, it asserts the kerr signal and decodes the
value to an arbitrary number.
1
The decoder flags the 10B_ERR characters as invalid codes and asserts the
kerr signal.
When the idle_del signal is asserted, it deletes all 10-bit words identified as the
special IDLE character of K28.5.
8B10B Encoder/Decoder MegaCore Function User Guide
May 2011 Altera Corporation
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